Testing is an important step in the production of semiconductor devices. One type of test is referred to as a High Temperature Operating Lifetime (HTOL) test. IC manufacturers can use HTOL testing to evaluate reliability of their devices and to guarantee that their devices are capable of operating at a desired performance level over a defined period of time (e.g., 10 years). In HTOL testing, IC devices are operated under a higher junction temperature (Tj) than the maximum allowable junction temperature for normal usage of the IC devices by customers. “Junction temperature” is defined as the temperature of the actual semiconductor die of an IC. Operating the devices under a higher junction temperature accelerates the reliability mechanism used to assess reliability of the IC devices up to an end of lifetime within a reasonable test time.
A conventional technique for HTOL testing involves testing IC devices in a “burn-in” chamber. The ambient temperature of the “burn-in” chamber is controlled using hot air flow to elevate the junction temperatures of the IC devices beyond their maximum specified junction temperatures while the IC devices are electrically tested. However, this method of testing does not provide for precise control of temperature, since the temperature in the “burn-in” chamber may fluctuate by plus/minus five degrees Celsius throughout the burn-in test. Furthermore, due to the nature of modern semiconductor fabrication and assembly process, device-to-device variation among the IC devices can result in a wide range in power consumption across the different IC devices being tested. A “burn-in” chamber does not compensate for such variations among IC devices being tested and thus IC devices are stressed with different junction temperatures based on their individual levels of power consumption. The aforementioned temperature control problems can result in a significant increase to the risk of having destructive thermal run-away during burn-in. Further, the temperature control problems deteriorate the accuracy of the test results.
Another problem with conventional burn-in testing is the inaccuracy added to the test results due to the junction temperature being estimated either based on power consumption of the ICs under test or temperature of the IC packages. In either case, the junction temperature (i.e., the temperature of the IC die) is not directly measured. Thus, a junction-to-ambient or junction-to-case thermal resistance must be characterized independently from the burn-in test in order to derive a measurement of junction temperature. A small error in thermal resistance used in the calculation can translate to a significant error in test results.
Accordingly, there exists a need in the art for an improved method and apparatus for burn-in of an IC.